1. Field of the Invention
The present invention relates to a semiconductor device. In particular, the invention relates to a semiconductor device capable of preventing electrostatic breakdown with an internal power supply protective element connected with a branch line.
2. Description of Related Art
In recent years, semiconductor integrated circuits have made a progress toward miniaturizing elements to improve a function and performance of a device. However, a semiconductor device composed of miniaturized elements has a problem that the device is easily broken when being subjected to electrostatic discharge (ESD). If an element is subject to the ESD, a surge (for example, abnormal voltage and current) is applied to the element. The breakdown of a semiconductor element due to the surge implies ESD breakdown. A semiconductor integrated circuit device is thus required to withstand the ESD breakdown. The principle of the ESD breakdown of the element is disclosed in IEEE Transactions on electron devices, vol. 35, No. 12, 1998, pp. 2133-2139, CHARVAKA DUVVURY et al. ‘Internal Chip ESD Phenomena Beyond the Protection Circuit’.
As disclosed in IEEE Transactions on electron devices, vol. 35, No. 12, 1998, pp. 2133-2139, CHARVAKA DUVVURY et al. ‘Internal Chip ESD Phenomena Beyond the Protection Circuit’, even though a surge current is prevented from flowing into an internal circuit by use of a power supply protective element connected between a power supply and a ground terminal to suppress a voltage applied to the internal circuit, elements of the internal circuit cannot be protected from breakdown. That is, even if the power supply protective element prevents a surge current from flowing into the internal circuit, short-circuiting occurs between a gate and a drain of a MOSFET unless a surge current flows through an expected path. FIG. 10 shows a surge current path in the case where a surge current is supplied from a power supply terminal to flow into a ground terminal by way of an internal circuit. In the illustrated example of FIG. 10, an internal circuit 1001 breaks down. FIG. 11 shows a surge current path where a surge current is supplied from an input/output terminal of a semiconductor device to flow into a power supply terminal by way of an internal circuit. Also in the illustrated example of FIG. 11, the internal circuit 1101 breaks down.
To that end, many input protective elements and circuits, output protective elements and circuits, and power supply protective elements and circuits have been proposed for increasing an ESD breakdown voltage. A diode, a gg-NMOS (grounded gate-NMOS), and an SCR (silicon controlled rectifier) have been generally used as the power supply protective elements. These power supply protective elements function to discharge a surge current to paths outside the internal circuit to suppress a voltage applied to the internal circuit when a surge is applied to a device. Further, as a countermeasure against a surge applied during the device operation, an active power supply protective element that discharges a surge current to paths outside the internal circuit to prevent a voltage increase of the internal circuit upon the device operation is used in some cases.
However, there is a problem that the protective element cannot exert a protective function sufficiently depending on the layout of the power supply protective elements. FIGS. 12A to 12F schematically show a conventional layout of protective elements. FIG. 13 shows a schematic two-dimensional layout of conventional protective elements. The conventional power supply protective elements dispose typically a portion near the semiconductor device terminal and main wiring thereof.
Based on the above, Japanese Unexamined Patent Application Publication No. H02-307258 discloses a technique of dispose power supply protective elements at both of a portion near a terminal and a portion near an internal circuit if wiring lines of the semiconductor device have impedance. However, Japanese Unexamined Patent Application Publication No. H02-307258 discloses no specific layout of the protective elements, so the layout depends on designer's know-how. Further, Japanese Unexamined Patent Application Publication Nos. H03-72666 and H04-48773 disclose a technique of connecting not only between a power supply terminal and a ground terminal but other terminals using the power supply protective elements. However, even the technique disclosed in Japanese Unexamined Patent Application Publication Nos. H03-72666 and H04-48773 has a problem in that the internal circuit cannot be reliably protected since the power supply protective elements are arranged merely around the terminals of the semiconductor device. Japanese Unexamined Patent Application Publication Nos. H03-27566 and H11-297939 disclose a technique of connecting between a power supply line and a ground line using plural power supply protective elements to reduce an apparent impedance of the power supply protective elements. However, even the techniques disclosed in Japanese Unexamined Patent Application Publication Nos. H03-27566 and H11-297939 face a problem that it is difficult to protect the device from a surge current flowing through a narrow branch line that branches off from a thick main wiring line directly connected with a semiconductor device power supply terminal and a ground terminal thereof.
As a result of verifying the above problems by experiment using a circuit of FIG. 14, in the case of applying a surge between VCC1 pad and GND1 pad by use of a TLP (transmission line pulse) device, an internal inverter group 1401 does not break. However, in the case of applying a surge between VCC2 pad and GND2 pad, the ESD breakdown voltage drops down to 55% of that obtained by applying the surge between VCC1 pad and GND1 pad. In order to obtain a uniform breakdown voltage whichever terminal is used to apply a surge, a gate oxide film should be formed with a large thickness.
Further, in a CDM (charged device model) test for changing a device and then releasing charges from the device, charges are accumulated in an internal element, so a discharge path of the charges is hardly predicted. In the ESD applying test such as a CDM test, a discharge path of charges accumulated in the element includes other elements than the power supply protective elements around the terminal. Thus, even with the above related art, the elements cannot be sufficiently protected.